Fault tree
| Fault tree |
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| See also |
Fault tree – it is a logic diagram used to analyze the evaluation of accuracy and security. It is conventional in various sectors from the chemical and railway industry for the amelioration of carriage design and software sureness. Mainly, its reputed is gained when integrated with the vent tree analysis as a part of the probabilistic safety assessment (PSA) [1].
In an opinion of Ming-Hung Shu, Ching-Hsue Cheng, Jing-Rong Chang: It uses clear graphics to vividly give visibility to fault dependencies between the part/component faults and the manufacturing system/process fault.
The fault tree may evidently note points of the system/process related to considerable failures. Furthermore, it can also be seen whether a piece/component flaw will cause a scheme/procedure fault, what the result is, how great the result is, and its system. A fault tree is an obvious demonstration for those management and allowance personnel who have never taken part in the scheme/procedure conception and trial-manufacture, which will greatly shorten the training period of the allowance personnel, and therefore cut down the cost for personnel training. The qualitative analysis of fault trees a scheme/procedure may make the authors with an insight into the scheme/procedure attitude, so as to be capable to find out the deficient links in the design scheme, and take corrective measures[2].
An overview of fault tree analysis
Watson was the first person who in 1961 used the classic fault tree analysis. This diagram "consisting of a top event and a structure delineating how the top event may occur. Up to now, the scope of conventional FTA has expanded from the aviation/space industry and nuclear industry to [3]:
- electronics,
- electric power
and the chemical industry as well as
- mechanical engineering,
- traffic,
- architecture, etc.
The trailblazing work on a blurred fault tree analysis belongs to Tanaka. He treated probabilities of Basic events as trapezoidal blurred numbers and applied the blurred expansion concept to calculate the possibility of the top event. Concurrently, he specified an indicator function comparables to importance benchmarks for appraising what extent a primary case cooperates to the top event.
Combinations of the undesired events
According to M. Cepin and B.Mavko: The fault tree is a tool to identify and assess all combinations of the undesired events in the context of the system operations and its environment that can lead to the undesired state of the system.
A top event stood for the undesired state of the system. The logical gates assimilate the elementary events to the top event. The elementary events are the events, which are not further developers, e.g. the basic events and the house events. The basic events are the fundamental elements of the fault tree, which represent the undesired events, e.g. the item failures, the missed operation indications, the human mistakes, the inaccessibility due to the test and maintenance actions, the usual causa involvements. The house events represent the situations set either to true or false, which support the modeling of relations between the gates and the basic events and entitle that the fault tree better represents the system operations and its environment[4].
Footnotes
References
- Čepin M., Mavko B. (2012), A dynamic fault tree, "Reliability Engineering & System Safety", 75(1), 83–91
- Ferdous R., Khan F., Sadiq R., Amyotte P., Veitch B. (2011), Fault and Event Tree Analyses for Process Systems RiskAnalysis: Uncertainty Handling Formulations, "Risk Analysis", Vol. 31, No. 1
- Helmer G., Wong J., Slagell M., Honavar V., Miller L., Lutz L. (2012), A Software Fault Tree Approach to Requirements Analysis of an Intrusion Detection System, "Requirements Engineering", 7:207–220
- Huang H.-Z, Tong H., Zuo M.-J. (2004), Posbist fault tree analysis of coherent systems, "Reliability Engineering & System Safety", 84(2), 141–148.
- Rotschild M., (2004), Fault Tree and Layer of Protection Hybrid Risk Analysis, "Process Safety Progress", Vol.23, No.3
- Shu M.-H., Cheng C.-H., Chang J.-R. (2006), Using intuitionistic fuzzy sets for fault-tree analysis on printed circuit board assembly, "Microelectronics Reliability", 46(12), 2139–2148.
Author: Dominika Pałkowska
